1. Field
Exemplary embodiments of the present invention relate to a semiconductor device having an array e-fuse, and more particularly, to a power gating technique for controlling power that is supplied to an array e-fuse.
2. Description of the Related Art
In general, each of a PMOS transistor and an NMOS transistor included in a dynamic random access memory (DRAM) has a threshold voltage Vth. Thus, an external voltage VDD equal to or more than 2*Vth corresponding to a sum of the threshold voltages of the PMOS transistor and the NMOS transistor should be basically secured to stabilize an operation region. Therefore, the DRAM requires a power-up signal generator to generate a power-up signal PWRUP indicating that the external voltage VDD reaches a required voltage level. The power-up signal generator outputs the power-up signal PWRUP that pulses to a logic high level once when the voltage level of the external voltage VDD is equal to or higher than a predetermined voltage level or a target voltage level and the external voltage VDD is stabilized. In response to the power-up signal PWRUP, an internal circuit performs an operation with the stabilized external voltage VDD. With high integration of semiconductor devices, a chip size of the device has been reduced and the operating voltage has also been reduced. Furthermore, a deep power down mode has been employed to reduce undesired power consumption.
Electrical fuses arranged in an array inside a semiconductor device are referred to as an array e-fuse. During a boot-up operation, all of data of the array e-fuse are read and stored in an internal latch for a power-up time after application of the external power supply voltage VDD. For the boot-up operation, it is required to read all of data stored in the array e-fuse before the semiconductor device starts performing a normal operation. In a case of a conventional metal fuse, fuse data is automatically stored in a latch during the boot-up operation depending on whether or not the metal fuse was cut. In a case of the array e-fuse, however, a boot-up read operation needs to be performed once at a time to read data on each cell or e-fuse during the boot-up operation. The boot-up operation needs to be performed within the power-up time that is a setup time for operation of the semiconductor device. Thus, the amount of fuse data to be read at a time becomes greater as the size of the array e-fuse becomes greater. In the case of a semiconductor device including the array e-fuse, the threshold voltage of which is relatively low, current consumption needs to be reduced. Therefore, when the semiconductor device includes transistors operating at a low voltage, that is, having low threshold voltages Vth, the semiconductor device may be operated at high speed, but current leakage may be increased. As a result, since the current leakage increases during a normal operation of the semiconductor device, additional current consumption occurs when the array e-fuse is used.